SystemVerilog Cheatsheet

1. cd to folder
2. vlib work on first run
3. vlog <filename>.sv to compile all relevant .sv files
4. vsim <testbench-name> to run your file (usually a testbench)
5. add wave sim:/<testbench-name>/uut/*
6. Run your simulation using either:
   1. run <N> to run for <N> nanoseconds
   2. run -all to automatically stop testbench when completed
7. vlog to recompile relevant modules as needed
8. restart -f to restart your simulation

To run .tcl scripts, use source <script-name>.tcl.

1. Navigate to your project directory using cd.
   The path should:
   • Use these slashes: ’/’
   • Use English characters
   • Not have any spaces (alternatively, it use quotes “”)
     
2. Create a ’work’ library using the command vlib work.
   • This is supposedly mandatory.
   • Only needs to be performed while running your project for the first time.
     
3. Compile your .sv files using vlog
   • If some files depend on modules from other files, You will have to compile these files first.
     
4. When running testbench, recompile relevant modules as needed using vlog
   • You only need to recompile the relevant modules.
   • No need to recompile the testbench itself or any other modules.

• Everything you write in SystemVerilog must be inside a module.

• A module is a fundemental building block that receives inputs and generates outputs.

  

  Here’s an example module:

  // [a,b] -> [my_module] -> [result = (a AND b)]
  module my_module(
     // Input and Output Declaration
     input logic  a,
     input logic  b,
     output logic result);
     // Declarations of "f"
      assign result = a & b;
  endmodule
  

• Allows to pass parameters to a module per-instantiation.
• Note: different from logic inputs and outputs.

Connect a wire to some combinatorical logic or another wire.

In SystemVerilog, a bit can take the following logical values:

The logic data type represents a wire (1 bit):

logic a,b,c,d,e;

Declaration of an 8-bit logic vector:

logic [7:0] w1; //w1[7] is the MSB

Here’s how you’d describe the “selector” wires in a mux module declaration:

module mux4tol(
               output logic O,
               input logic D0,
               input logic D1,
               input logic D2,
               input logic D3,
               input logic E,
               input logic [1:0] S
);
   // declarations
   // description of a mux
endmodule

Format: <width’><signed><radix> value

You can use this format to generate:

• Multiple bit integers (<width'>)
• Two’s complement negative numbers (<signed>)
• Write a number in base 2,8,10 or 16 (<radix>)

An enum type defines a set of named values. We will use enum for FSM state declaration:

logic [7:0] out;
logic [3:0] A;
out = {{4{1'b0}}, A[3:0]};

typedef enu​m {idle_st, state1, state2} state_type;

The following logic gates are available for direct instantiation:

• and
• or
• not
• xor
• nand
• nor
• xnor

Syntax:

gateName(output, input1, <optional_input2>)

Used in procedural blocks.

Using posedge, you can sample a value when your clock is on a positive edge.

This is an example that uses posedge to emulate a Flip-Flop:

logic a, in;
always_ff @(posedge clk) begin
   a <= in;
end

Only occurs on positive edge. This is how you implement it:

always_ff @(posedge clk) begin
   if (rst == 1'b1) begin
      <reset statement1>;
   end
   else begin
      <sync statement2>;
   end
end

Can occur whenever the reset entrance rises. This is how you implement it:

always_ff @(posedge clk, posedge rst) begin
   if (rst == 1'b1) begin
      <reset statement1>;
   end
   else begin
      <sync statement2>;
   end
end

This is how you implement a

This is how you can use the current state to infer outputs and the next state:

always_comb begin
   // Default assignments
    next_state = current_state;
    output1 = 1'b0;
    ...
    outputN = 1'b0

    // Specific assignments
      case (current_state)
        idle_st: begin
           next_state = ...;
           ouput1 = ...;
           ...
           outputN = ...;
        end
        start_st: begin
           next_state = ...;
           output1 = ...;
           ...
           outputN = ...;
        end
        ...
      endcase
end

A testbench generates input values and checks our Unit Under Test (UUT) for its response.

The UUT in our case is our module.

initial begin
   data = 0;
   #50 // Wait 50ns
   data = 1;
   #30 // Wait 30ns
   data = 0;
end

Here’s a working example:

// _tb stands for _testbench
module HalfAdder_tb;
   // Definition of testbench input values to UUT
   logic ha_a;
   logic ha_b;
   logic ha_sum;
   logic ha_carry;

   // Instance of UUT
   HalfAdder uut(
    .a(ha_a),
    .b(ha_b),
    .sum(ha_sum),
    .carry(ha_carry)
   );

   // Generate test input values here
   initial_begin
     ha_a = 0;
     ha_b = 0;

     #20
     ha_a = 1;
     ha_b = 0;

     #20
     ha_a = 1;
     ha_b = 1;
   end

endmodule

Used in an initial block to repeat statements.

repeat(num_of_times) begin
   <statement1>;
   <statement2>;
end

This is how you generate a clock signal for simulation 2:

// Start value of clock
initial begin
   Clock = 1'b0;
end

// Clock behavior
always begin
   #10 Clock = ~Clock;
end

Example: Waiting for 4 clock cycles

initial begin
   repeat(4) begin
      @(posedge clk);
   end
end

• Always add the current and next state to the waveform
• Given the current state and the inputs, check that the next state and output are as expected
• As always, search for x and z values and ensure they make sense